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LTC3878 1 3878f typical application features applications description fast, wide operating range no r sense tm step-down controller n distributed power systems n embedded computing n communications infrastructure l , lt, ltc and ltm are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6100678, 6580258, 5847554, 6304066. n wide v in range: 4v to 38v n 1% 0.8v voltage reference n extremely fast transient response n t on(min) : 43ns n valley current mode control n stable for low esr ceramic c out n no sense resistor required n optimized for high step-down ratios n pin compatible with the ltc1778 (no extv cc pin) n power good output voltage monitor n dual n-channel mosfet synchronous drive n adjustable switching frequency n programmable current limit with foldback n programmable soft-start n output overvoltage protection n small 16-pin narrow ssop package the ltc ? 3878 is a synchronous step-down switching regulator controller optimized for high switching frequency and fast transient response. the constant on-time valley current mode architecture allows for a wide input range, including very low duty factor operation. no external sense resistor or slope compensation is required. the LTC3878 is pin compatible with the ltc1778 in applications that do not use extv cc while offering better ef? ciency. consult with the factory to verify compatibility. operating frequency is set by an external resistor and compensated for variations in v in to offer excellent line stability. discontinuous mode operation provides high ef? ciency during light load conditions. a forced continu- ous control pin allows the user to reduce noise and rf interference. safety features include output overvoltage protection and programmable current limit with foldback. soft-start capability for supply sequencing is accomplished through an external timing capacitor. the current limit is user programmable. the LTC3878 allows operation from 4v to 38v at the input and from 0.8v to 90% v in at the output. the LTC3878 is available in a small 16-pin narrow ssop package. high ef? ciency step-down converter ef? ciency vs load current i on v in run/ss i th v rng sgnd fcb pgood tg bg pgnd v fb sw boost intv cc 0.22f 0.1f 120pf rjk0305 rjk0330 0.56h 432k 20k LTC3878 3878 ta01a 5.11k 10k v out 1.2v 15a v in 4.5v to 28v 4.7f 750f 10f load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3878 g07 0 0.1 continuous mode discontinuous mode v in = 12v v out = 1.2v sw freq = 400khz figure 7 circuit
LTC3878 2 3878f absolute maximum ratings input supply voltage (v in ) ......................... ?0.3v to 40v i on voltage ................................................. ?0.3v to 40v boost voltage .......................................... ?0.3v to 46v sw voltage ................................................... ?5v to 40v intv cc , (boost-sw), run/ss, pgood voltages .......................................... ?0.3v to 6v fcb, v rng voltages .................... ?0.3v to intv cc + 0.3v v fb , i th voltages ....................................... ?0.3v to 2.7v operating temperature range (note 4).... ?40c to 85c junction temperature (note 2) ............................. 125c storage temperature range ................... ?65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) gn package 16-lead plastic ssop narrow 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 run/ss pgood v rng fcb i th sgnd i on v fb boost tg sw pgnd bg intv cc v in nc t jmax = 125c, = = ( ) = = ( ) = ( ) = () = ( ) = = = () = = =
LTC3878 3 3878f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j is calculated from the ambient temperature t a and power dissipation p d as follows: t j = t a + (p d ? 110c/w) note 3: the LTC3878 is tested in a feedback loop that adjusts v fb to achieve a speci? ed error ampli? er output voltage (i th ). symbol parameter conditions min typ max units t off(min) minimum off-time i on = 30a 220 300 ns v sense(max) valley current sense threshold v pgnd C v sw peak current = valley + ripple v rng = 1v, v fb = 0.76v v rng = 0v, v fb = 0.76v v rng = intv cc , v fb = 0.76v l l l 108 74 152 133 93 186 165 119 224 mv mv mv v sense(min) minimum current sense threshold v pgnd C v sw forced continuous operation v rng = 1v, v fb = 0.84v v rng = 0v, v fb = 0.84v v rng = intv cc , v fb = 0.84v C67 C47 C93 mv mv mv v run/ss run/ss pin on threshold v run/ss rising 1.4 1.5 1.6 v soft-start charging current v run/ss = 0v C1.2 a intv cc(uvlo) intv cc undervoltage lockout falling l 3.3 3.9 v intv cc(uvlor) intv cc undervoltage lockout release rising l 3.6 4 v tg driver pull-up on-resistance tg high 2.5 tg driver pull-down on-resistance tg low 1.2 bg driver pull-up on-resistance bg high 2.5 bg driver pull-down on-resistance bg low 0.7 tg rise time c load = 3300pf (note 5) 20 ns tg fall time c load = 3300pf (note 5) 20 ns bg rise time c load = 3300pf (note 5) 20 ns bg fall time c load = 3300pf (note 5) 20 ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver (note 5) 15 ns tg/bg t 2d bottom gate off to top gate on delay synchronous switch-on delay time c load = 3300pf each driver (note 5) 15 ns internal v cc regulator internal v cc voltage 6v < v in < 38v 5.15 5.3 5.45 v internal v cc load regulation i cc = 0ma to 20ma C0.1 2 % pgood output pgood upper threshold v fb rising 5.5 7.5 9.5 % pgood lower threshold v fb falling C5.5 C7.5 C9.5 % pgood hysteresis v fb returning 2 3.5 % pgood low voltage i pgood = 5ma 0.15 0.4 v pgood turn-on delay 12 s electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 15v unless otherwise noted. note 4: the LTC3878e is guaranteed to meet speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3878i is guaranteed to meet speci? cations over the full C40c to 85c operating temperature range. note 5: rise and fall time are measured using 10% and 90% levels. delay times are measured using 50% levels.
LTC3878 4 3878f typical performance characteristics transient response fcm (forced continuous mode) transient response fcm positive load step transient response fcm negative load step transient response dcm (discontinuous mode) normal start-up, run/ss release from zero start-up v in cycled low and high ef? ciency vs load current ef? ciency vs input voltage frequency vs input voltage v in (v) 4 50 efficiency (%) 60 70 80 8 12 16 20 3878 g08 24 90 100 55 65 75 85 95 28 1a ccm 15a ccm 1a dcm v out = 1.2v sw freq = 400khz figure 7 circuit v in (v) 4 300 frequency (khz) 320 340 360 380 420 8 12 16 20 3878 g09 24 28 0a 15a 400 310 330 350 370 410 390 v out = 1.2v figure 7 circuit v out (ac) 50mv/div i l 10a/div i load 10a/div 50s/div load step 0a to 10a to 0a v in = 12v v out = 1.2v fcb = 0v sw freq = 400khz figure 7 circuit 3878 g01 v out (ac) 50mv/div v sw 20v/div i l 10a/div i load 10a/div 5s/div load step 0a to 10a v in = 12v v out = 1.2v fcb = 0v sw freq = 400khz figure 7 circuit 3878 g02 v out (ac) 50mv/div v sw 20v/div i l 10a/div i load 10a/div 5s/div load step 10a to 0a v in = 12v v out = 1.2v fcb = 0v sw freq = 400khz figure 7 circuit 3878 g03 v out (ac) 50mv/div i l 10a/div i load 10a/div 50s/div load step 1a to 11a to 1a v in = 12v v out = 1.2v fcb = intv cc sw freq = 400khz figure 7 circuit 3878 g04 v out 500mv/div i l 10a/div run/ss 2v/div 50ms/div v in = 12v v out = 1.2v fcb = 0v sw freq = 400khz figure 7 circuit 3878 g05 v out 1v/div v in 10v/div i l 10a/div run/ss 5v/div 100ms/div v in = 12v v out = 1.2v fcb = 0v sw freq = 400khz figure 7 circuit 3878 g06 load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3878 g07 0 0.1 continuous mode discontinuous mode v in = 12v v out = 1.2v sw freq = 400khz figure 7 circuit
LTC3878 5 3878f typical performance characteristics frequency vs load current load regulation fcm i th voltage vs load current current sense voltage vs i th voltage on-time vs i on current current limit foldback maximum v ds current sense threshold vs v rng voltage maximum v ds current sense threshold vs run/ss voltage foldback reference voltage vs temperature load current (a) 0 i th voltage (v) 1.7 2.1 2.5 20 3878 g12 1.3 0.9 1.5 1.9 2.3 1.1 0.7 0.5 5 10 15 25 continuous mode discontinuous mode v in = 15v v out = 1.2v figure 7 circuit i on current (a) 1 10 on-time (ns) 100 1000 10000 10 100 3878 g14 figure 7 circuit v fb (v) 0 80 100 140 0.6 3878 g15 60 40 0.2 0.4 0.8 20 0 120 maximum current sense threshold (mv) v rng = 1v figure 7 circuit v rng voltage (v) 0.2 0 maximum current sense thresold (mv) 50 150 200 250 0.6 1.0 1.2 2.0 3878 g16 100 0.4 0.8 1.4 1.6 1.8 300 run/ss voltage (v) 1.5 140 120 100 80 60 40 20 0 3878 g17 2.0 2.5 3.0 maximum current sense threshold (mv) temperature (c) C50 feedback reference voltage (v) 0.800 0.802 0.804 110 3878 g18 0.798 0.796 0.792 C10 30 70 C30 10 50 90 0.794 0.808 0.806 i load (a) 0 frequency (khz) 250 330 410 2468 3878 g10 170 90 210 290 370 130 50 10 10 12 14 continuous mode discontinuous mode v in = 15v v out = 1.2v figure 7 circuit load current (a) 0 $ v out (%) C0.10 C0.08 C0.06 3878 g11 C0.12 C0.14 C0.16 510 C0.04 C0.02 0 15 v in = 15v v out = 1.2v figure 7 circuit i th voltage (v) 0 C150 current sense threshold (mv) C100 0 50 100 1 2 2.5 300 3878 g13 C50 0.5 1.5 150 200 250 v rng = 0.2v v rng = 0.5v v rng = 1.0v v rng = 1.5v v rng = 2.0v
LTC3878 6 3878f typical performance characteristics error ampli? er g m vs temperature shutdown current vs input voltage quiescent current vs intv cc intv cc load regulation intv cc dropout intv cc vs i load ef? ciency: LTC3878 vs ltc1778 run/ss pin current vs temperature input voltage (v) 510 10 input current (a) 20 35 15 25 30 3878 g20 15 30 25 20 35 40 intv cc load current (ma) 0 $ intv cc (%) C0.8 C0.4 0 40 3878 g22 C1.2 C1.6 C1.0 C0.6 C0.2 C1.4 C1.8 C2.0 10 20 30 50 intv cc load current (ma) 0 C1200 intv cc dropout voltage (mv) C1000 C800 C600 C400 C200 0 10 20 30 40 3878 g23 50 v in = 4.5v temperature (c) C50 1.0 g m (ms) 1.1 1.3 1.4 1.5 2.0 1.7 0 50 3878 g19 1.2 1.8 1.9 1.6 100 intv cc (v) 4.0 quiescent current (ma) 1.5 2.0 2.5 5.5 6.5 3878 g21 1.0 0.5 0 4.5 5.0 6.0 3.0 3.5 4.0 7.0 i load (ma) 0 1 0 intv cc (v) 2 3 4 5 6 50 100 150 200 3878 g24 intv cc i load rising intv cc i load falling do not exceed 50ma continuous i limit = 150ma, intv cc > 0.7v i limit = 22ma, intv cc < 0.7v load current (a) 0 90 92 94 20 3878 g25 88 86 51015 25 84 82 80 efficiency (%) 1.6% LTC3878 ltc1778 q t = rjk0305dpb q b = rjk0330dpb l = pulse pa0513.441nlt f sw = 300khz v in = 12v v out = 1.2v temperature (c) C50 run/ss pin current (a) 1.2 1.4 3878 g26 1.0 0.8 0 50 100 1.6 v in = 15v v out = 1.2v fcb = intv cc
LTC3878 7 3878f pin functions run/ss (pin 1): run control and soft-start input. a capacitor to ground on this pin sets the ramp time to full output current (approximately 3s/f) when run/ss is open. the switching outputs are disabled when below 1.5v. the device is in micropower shutdown when under 0.7v. if left open, there is an internal 1.2a pull-up current on run/ss. intv cc is enabled when run/ss exceeds 0.7v. pgood (pin 2): power good output. this open-drain logic output is pulled to ground when the output voltage is outside of a 7.5% window around the regulation point. v rng (pin 3): v ds sense voltage range input. the maxi- mum allowed bottom mosfet v ds sense voltage between sw and pgnd is equal to (0.133)v rng . the voltage applied to v rng can be any value between 0.2v and 2v. if v rng is tied to sgnd, the device operates with a peak sense voltage that is equivalent to a v rng of 0.7v. if v rng is tied to intv cc , the device operates with a peak sense voltage that is equivalent to a v rng of 1.4v. fcb (pin 4): forced continuous input. connect this pin to intv cc to enable discontinuous mode for light load operation. connect this pin to sgnd to force continuous mode operation in all conditions. i th (pin 5): current control threshold and error ampli? er compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v, with 0.8v corresponding to zero sense voltage (zero current). sgnd (pin 6): signal ground. all small-signal components should be connected to sgnd. connect sgnd to pgnd using a single pcb trace. i on (pin 7): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thus the switching frequency. v fb (pin 8): error ampli? er feedback input. this pin con- nects the error ampli? er to an external resistive divider from v out . nc (pin 9): for factory use only. can be connected to any voltage equal to or less than intv cc . v in (pin 10): main input supply. the supply voltage can range from 4v to 38v. for increased noise immunity de- couple this pin to pgnd with an rc ? lter. intv cc (pin 11): internal 5.3v regulator output. the driver and control circuits are powered from this voltage. decouple this pin to pgnd with a minimum of 1f, 10v x5r or x7r ceramic capacitor. bg (pin 12): bottom gate drive. this pin drives the gate of the bottom n-channel power mosfet between pgnd and intv cc . pgnd (pin 13): power ground. connect this pin as close as practical to the source of the bottom n-channel power mosfet, the (C) terminal of c intvcc and the (C) terminal of c vin . sw (pin 14): switch node. the (C) terminal of the bootstrap capacitor, c b , connects to this node. this pin swings from a diode voltage below ground up to v in . tg (pin 15): top gate drive. this pin drives the gate of the top n-channel power mosfet between sw and boost. boost (pin 16): boosted floating driver supply. the (+) terminal of the bootstrap capacitor, c b , connects to this node. this node swings from (intv cc C v schottky ) to v in + (int vcc C v schottky ).
LTC3878 8 3878f functional diagram 15 switch logic ov run fcnt r dss 20k r on tg 14 sw 16 boost v fb r1 fcb i on 0.8v 12 bg 13 pgnd pg 0.86v 1.5v 1.2a current limit soft-start C90mv 1.16v 160a 0.8v r c c c1 1.7ms 2.4v neg clmp 3.3a pos clmp fcnt 0.6v 0.74v 3878 fd 11 intv cc c b c intvcc c out v out c vin v in d b mt mb C + C + C + C + C + f q s r t on = (10pf) ost 0.7v i on 8 pgood 2 sgnd 6 r2 5.3v ldo 0.8v ref 4 7 v in 10 i cmp i rev v rng 3 i th 5 ov uv C + C + + C + C + C + C C C s v rng 1.4v 0.7v s 4 ea run 1 240k c ss run/ss 1
LTC3878 9 3878f operation ltc1778 compatibility the LTC3878 is compatible with the ltc1778 in applica- tions which do not use the extv cc function. the LTC3878 offers improved gate drive and reduced dead time, which allows higher ef? ciency than the ltc1778. on the ltc1778 pin 9 is extv cc , but on the LTC3878 it is a no connect. the other notable difference is that the shutdown latch- off timer is removed. the LTC3878 should be a drop in, pin-for-pin replacement in most applications that do not use extv cc . the LTC3878 should be tested and veri? ed in each application without assuming compatibility. con- tact a linear applications expert to answer any questions regarding LTC3878/ltc1778 compatibility. main control loop the LTC3878 is a valley current mode controller ic for use in dc/dc step-down converters. in normal continu- ous operation, the top mosfet is turned on for a ? xed interval determined by a one-shot timer, ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current comparator, i cmp , trips, restarting the one-shot timer and initiating the next cycle. inductor valley current is measured by sensing the voltage between the pgnd and sw pins using the bottom mosfet on- resistance. the voltage on the i th pin sets the compara- tor threshold corresponding to inductor valley current. the error ampli? er ea adjusts this voltage by comparing the feedback signal v fb from the output voltage to the feedback reference voltage v fbref . increasing the load current causes a drop in the feedback voltage relative to the reference. the ea senses the feedback voltage drop and adjusts the i th voltage higher until the average inductor current matches the load current. with dc current loads less than 1/2 of the peak-to-peak ripple the inductor current can drop to zero or become negative. in discontinuous operation, negative inductor current is detected and prevented by the current reversal comparator i rev , which shuts off mb. both switches remain off with the output capacitor supplying the load current until the ea moves the i th voltage above the zero current level (0.8v) to initiate another switching cycle. when the fcb (forced continuous bar) pin is below the internal fcb threshold reference, v fcb , the regulator is forced to operate in continuous mode by disabling reversal comparator, i rev , thereby allowing the inductor current to become negative. the continuous mode operating frequency can be deter- mined by dividing the calculated duty cycle, v out /v in , by the ? xed on-time. the ost generates an on-time proportional to the ideal duty cycle, thus holding the frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor, r on . foldback current limiting is provided to protect against low impedance shorts. if the controller is in current limit and v out drops to less 50% of regulation, the current limit set-point folds back to progressively lower values. to recover from foldback current limit, the excessive load or low impedance short needs to be removed. pulling the run/ss pin low forces the controller into its shutdown state, turning off both mt and mb. releasing the pin allows an internal 1.2a current source to charge up an external soft-start capacitor, c ss . when the run/ ss pin is less than 0.7v, the device is in the low power shutdown condition with a nominal bias current of 18a. when run/ss is greater than 0.7v and less than 1.5v, intv cc and all internal circuitry are enabled while mt and mb are forced off. current-limited soft-start begins when run/ss exceeds 1.5v. normal operation at full current limit is achieved at approximately 3v on run/ss. foldback current limit is defeated during soft-start.
LTC3878 10 3878f applications information the basic LTC3878 application circuit is shown on the ? rst page of this data sheet. external component selection is largely determined by maximum load current and begins with the selection of sense resistance and power mosfet switches. the LTC3878 uses the on-resistance of the syn- chronous power mosfet to determine the inductor current. the desired ripple current and operating frequency largely determines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter, and c out is chosen with low enough esr to meet output voltage ripple and transient speci? cations. maximum v ds sense voltage and v rng pin inductor current is measured by sensing the bottom mosfet v ds voltage that appears between the pgnd and sw pins. the maximum allowed v ds sense voltage is set by the voltage applied to the v rng pin and is approxi- mately equal to (0.133)v rng . the current mode control loop does not allow the inductor current valleys to exceed (0.133)v rng . in practice, one should allow margin, to ac- count for variations in the LTC3878 and external component values. a good guide for setting v rng is: v rng = 7.5 ? (maximum v ds sense voltage) an external resistive divider from intv cc can be used to set the voltage on the v rng pin between 0.2v and 2v, resulting in peak sense voltages between 26.6mv and 266mv. the wide peak voltage sense range allows for a variety of applications and mosfet choices. the v rng pin can also be tied to either sgnd or intv cc to force internal defaults. when v rng is tied to sgnd, the device operates with a peak sense voltage that is equivalent to a v rng of 0.7v. when the v rng pin is tied to intv cc , the device operates with a peak sense voltage that is equivalent to a v rng of 1.4v. power mosfet selection the LTC3878 requires two external n-channel power mosfets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , re- verse transfer capacitance c rss and maximum current i ds(max) . the gate drive voltages are set by the 5.3v intv cc supply. consequently, logic-level threshold mosfets must be used in LTC3878 applications. if the input voltage is expected to drop below 5v, then sub-logic level threshold mosfets should be considered. using the bottom mosfet as the current sense element requires particular attention be paid to its on-resistance. mosfet on-resistance is typically speci? ed with a maxi- mum value r ds(on)(max) at 25c. in this case additional margin is required to accommodate the rise in mosfet on-resistance with temperature. r r ds on max sense t ()( ) = the t term is a normalization factor (unity at 25c) accounting for the signi? cant variation in on-resistance with temperature, typically about 0.4%/c, as shown in figure 1. for a maximum junction temperature of 100c using a value of t = 1.3 is reasonable. the power dissipated by the top and bottom mosfets depends upon their respective duty cycles and the load current. when the LTC3878 is operating in continuous mode, the duty cycles for the mosfets are: d v v d vv v top out in bot in out in = = C figure 1. r ds(on) vs temperature junction temperature (c) C50 r t normalized on-resistance () 1.0 1.5 150 3878 f01 0.5 0 0 50 100 2.0
LTC3878 11 3878f the resulting power dissipation in the mosfets at maxi- mum output current are: pdi r v top top out max top ds on max ??? () () ()() 2 i in out max miller tghigh intvc i c dr v 2 2 () () c c miller tglow miller osc bot bo v dr v f pd C t t out max bot ds on max ir ??? () () ()() 2 dr tghigh is pull-up driver resistance and dr tglow is the tg driver pull-down resistance. v miller is the miller ef- fect v gs voltage and is taken graphically from the power mosfet data sheet. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on the most data sheets (figure 2). the curve is generated by forcing a constant input current into the gate of a common source, current source, loaded stage and then plotting the gate versus time. the initial slope is the effect of the gate-to-source and gate-to-drain capacitance. the ? at portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capaci- tance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is ? at) is speci- ? ed from a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve speci? ed v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b or the parameter q gd on a manufacturers data sheet and divide by the speci? ed v ds test voltage, v ds(test) . c q v miller gd ds test () c miller is the most important selection criteria for deter- mining the transition loss term in the top mosfet but is not directly speci? ed on mosfet data sheets. both mosfets have i 2 r power loss, and the top mosfet includes an additional term for transition loss, which are highest at high input voltages. for v in < 20v, the high cur- rent ef? ciency generally improves with larger mosfets, while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher ef? ciency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. operating frequency the choice of operating frequency is a tradeoff between ef? ciency and component size. lowering the operating fre- quency improves ef? ciency by reducing mosfet switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. conversely, raising the operating frequency degrades ef? ciency but reduces component size. the operating frequency of LTC3878 applications is de- termined implicitly by the one-shot timer that controls the on-time, t on , of the top mosfet switch. the on-time is set by the current into the i on pin according to: t v i pf on ion = () 07 10 . tying a resistor r on from v in to the i on pin yields an on-time inversely proportional to v in . for a step-down converter, this results in pseudo ? xed frequency operation as the input supply varies. f v vr pf hz op out on = () 07 10 .? [] applications information figure 2. gate charge characteristic + C v ds v in 3878 f02 v gs miller effect q in ab c miller = (q b C q a )/v ds v gs v + C
LTC3878 12 3878f applications information figure 3 shows how r on relates to switching frequency for several common input votlages. when designing for pseudo ? xed frequency, there is sys- tematic error because the i on pin voltage is approximately 0.7v, not zero. this causes the i on current to be inversely proportional to (v in C 0.7v) and not v in . the i on current error increases as v in decreases. to correct this error, an additional resistor r on2 can be connected from the i on pin to the 5.3v intv cc supply. r vv v r on on 2 53 07 07 = .C. . likewise, the maximum frequency of operation is deter- mined by the ? xed on-time, t on , and the minimum off-time, t off(min) . the ? xed on-time is determined by dividing the duty factor by the nominal frequency of operation: f v vf t hz max out in op off min = + 1 ? ??[ ] () the LTC3878 is a pfm (pulse frequency mode) regula- tor where pulse density is modulated, not pulse width. consequently, frequency increases with a load step and decreases with a load release. the steady-state operating frequency, f op , should be set suf? ciently below f max to allow for device tolerances and transient response. inductor value calculation given the desired input and output voltages, the induc- tor value and operation frequency determine the ripple current: i v fl v v l out op out in = ? C 1 lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest ef? ciency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, ef? ciency and operating frequency. figure 4. maximum switching frequncy vs duty cycle r on (k) 100 100 switching frequency (khz) 1000 1000 10000 3878 f03 v out = 1.5v v out = 12v v out = 3.3v v out = 5v figure 3. switching frequency vs r on minimum off-time and dropout operation the minimum off-time, t off(min) , is the shortest time required for the LTC3878 to turn on the bottom mosfet, trip the current comparator and then turn off the bottom mosfet. this time is typically about 220ns. the minimum off-time limit imposes a maximum duty cycle of t on / (t on + t off(min) ). if the maximum duty cycle is reached, due to a drooping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: vv tt t in min out on off min on () () = + a plot of maximum duty cycle vs. frequency is shown in figure 4. duty cycle (v out /v in ) dropout region switching frequency (mhz) 2 3 3878 f04 1 0 0 0.25 0.50 0.75 1 4
LTC3878 13 3878f applications information a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a speci? ed maximum, the inductance should be chosen according to: l v fi v v out op il max out in max = ? C () () 1 once the value for l is known, the type of inductor must be selected. high ef? ciency converters generally cannot tolerate the core loss of low cost powdered iron cores, forcing the use of more expensive ferrite materials such as molypermalloy or kool m ? cores. a variety of inductors designed for high current, low voltage applications are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft, toko, vishay, pulse and wurth. inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a ? xed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! c in and c out selection the input capacitance c in is required to ? lter the square wave current at the drain of the top mosfet. use a low esr capacitor sized to handle the maximum rms current. ii v v v v rms out max out in in out () ?? C1 this formula has a maximum at v in = 2v out , where i rms = i out(max) /2. this simple worst-case condition is com- monly used for design because even signi? cant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life, which makes it advisable to de-rate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the v out is approximately bounded by: viesr fc out l op out + 1 8? ? since i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, specialty polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. specialty polymer capacitors offer very low esr but have lower speci? c capacitance than other types. tantalum capacitors have the highest speci? c capacitance but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have signi? cantly higher esr, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage co- ef? cient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signi? cant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. to dampen input voltage transients, add a small 5f to 40f aluminum electrolytic capacitor with an esr in the range of 0.5 to 2. high performance though-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recom- mended to reduce the effect of lead inductance.
LTC3878 14 3878f applications information top mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store approximately 100 times the gate charge required by the top mosfet. in most applications 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. it is recommended that the boost capacitor be no larger than 10% of the intv cc capacitor c vcc , to ensure that the c vcc can supply the upper mosfet gate charge and boost capacitor under all operating conditions. variable frequency in response to load steps offers superior tran- sient performance but requires higher instantaneous gate drive. gate charge demands are greatest in high frequency low duty factor applications under high di/dt load steps and at start-up. setting output voltage the LTC3878 output voltage is set by an external feed- back resistive divider carefully placed across the output, as shown in figure 5. the regulated output volt age is determined by: vv r r out b a 08 1 . to improve the transient response, a feed-forward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. discontinuous mode operation and fcb pin the fcb (forced continuous bar) pin determines whether the LTC3878 operates in forced continuous mode or al- lows discontinuous conduction mode. tying this pin above 0.8v enables discontinuous operation, where the bottom mosfet turns off when the inductor current reverses polarity. the load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary with changes in v in . in steady-state operation, discontinuous conduction mode occurs for dc load currents less than 1/2 the peak- to-peak ripple current. tying the fcb pin below the 0.8v threshold forces continuous switching, where inductor current is allowed to reverse at light loads and maintain synchronous switching. in addition to providing a logic input to force continuous operation, the fcb pin provides a means to maintain a ? y back winding output when the primary is operating in discontinuous mode. the secondary output v out2 is normally set as shown in figure 6 by the turns ratio n of the transformer. however, if the controller goes into discontinuous mode and halts switching due to a light primary load current, then v out2 will droop. an external resistor divider from v out2 to the fcb pin sets a minimum voltage v out2(min) below which continuous operation is forced until v out2 has risen above its minimum. vv r r out min 2 08 1 4 3 () . =+ figure 6. secondary output loop figure 5. setting output voltage LTC3878 v fb v out r b c ff r a 3878 f05 fcb sw tg si4884 3878 f06 LTC3878 bg r3 r4 pgnd sgnd si4874 v in c in c out c out2 v in v out2 v out 1n4148 ? ?
LTC3878 15 3878f applications information fault conditions: current limit and foldback the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the LTC3878, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current mode control, the maximum sense voltage and the sense re- sistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i v r i limit sns max ds on t l =+ () () ? ? 1 2 the current limit value should be checked to ensure that i limit(min) > i out(max) . the current limit value should be greater than the inductor current required to produce maximum output power at the worst-case ef? ciency. worst-case ef? ciency typically occurs at the highest v in and highest ambient temperature. it is important to check for consistency between the assumed mosfet junction temperatures and the resulting value of i limit which heats the mosfet switches. caution should be used when setting the current limit based on the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on-resistance. data sheets typically specify nominal and maximum values for r ds(on) but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same amount below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. to further limit current in the event of a short circuit to ground, the LTC3878 includes foldback current limiting. if the output fails by more than 50%, then the maximum sense voltage is progressively lowered to about one-sixth of its full value. intv cc regulator an internal p-channel low dropout regulator produces the 5.3v supply that powers the drivers and internal circuitry within the LTC3878. the intv cc pin can supply up to 50ma rms and must be bypassed to ground with a minimum of 1f low esr tantalum or ceramic capacitor (10v, x5r or x7r). output capacitance greater than 10f is discouraged. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers. applications using large mosfets with a high input voltage and high frequency of operation may cause the LTC3878 to exceed its maximum junction temperature rating or rms current rating. in continuous mode operation, this current is i gatechg = f op (q g(top) + q g(bot) ). the junction temperature can be estimated from the equations given in note 2 of the electrical characteristics. for example, with a 30v input supply, the LTC3878 is limited to less than 16.5ma: t j = 70c + (16.5ma)(30)(110c/w) = 125c using the intv cc regulator to supply external loads greater than 5ma is discouraged. intv cc is designed to supply the LTC3878 with minimal external loading. when using the regulator to supply larger external loads, carefully consider all operating load conditions. during load steps and soft-start, transient current requirements signi? cantly exceed the rms values. additional loading on intv cc takes away from the drive available to source gate charge during high frequency transient load steps. soft-start with the run/ss pin the run/ss pin both enables the LTC3878 and provides a means of programmable current limited soft-start. pulling the run/ss pin below 0.7v puts the LTC3878 into a low quiescent current shutdown (i q < 15a). releasing the pin allows an internal 1.2a current source to charge up the external timing capacitor c ss . if run/ss has been pulled all the way to ground, there is a delay before start- ing. this delay is created by charging c ss from ground to 1.5v through a 1.2a current source. t v a csfc delay ss ss == () 15 12 13 . . ?./ when the voltage on run/ss reaches 1.5v, the LTC3878 begins to switch. i th is clamped to be no greater than run/ss C 0.6v, and the device begins switching when i th exceeds 0.9v. as the run/ss voltage rises to 3v, the clamp on i th increases until it reaches the full-scale 2.4v limit after an additional delay of 1.3s/f. during this time, the soft-start current limit is set to: ii run ss v v v limit ss limit () ? /C. C. .C. = () 06 08 24 0 8 8v
LTC3878 16 3878f applications information regulator output current is negative when i th is between 0v and 0.8v and positive when i th is between 0.8v and the maximum full-scale set-point of 2.4v. in normal operating conditions the run/ss pin will continue to charge positive until the voltage is equal to intv cc . intv cc undervoltage lockout whenever intv cc drops below approximately 3.4v, the device enters undervoltage lockout (uvlo). in a uvlo condition, the switching outputs tg and bg are disabled. at the same time, the run/ss pin is pulled down from intv cc to 0.8v with a 3a current source. when the intv cc uvlo condition is removed, run/ss ramps from 0.8v and begins a normal current limited soft-start. this feature is important when regulator start-up is not initi- ated by applying a logic drive to run/ss. soft-start from intv cc uvlo release greatly reduces the possibility for start-up oscillations caused by the regulator starting up at intv cc(uvlor) and then shutting down at intv cc(uvlo) due to inrush current. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3878 circuits. 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the ef? ciency to drop at high output currents. in continuous mode the average output current ? ows though the inductor l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply by summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 and r l = 0.005, the loss will range from 15mw to 1.5w as the output current varies from 1a to 10a. 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is signi? cant at input voltages above 20v. 3. intv cc current. this is the sum of the mosfet driver and control currents. 4. c in loss. the input capacitor has the dif? cult job of ? lter- ing the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and suf? cient capacitance to prevent the rms current from causing ad- ditional upstream losses in fuses or batteries. other losses, which include the c out esr loss, bottom mosfet reverse recovery loss and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve ef? ciency, the input current is the best indicator of changes in ef? ciency. if you make a change and the input current decreases, then the ef? ciency has increased. if there is no change in input current there is no change in ef? ciency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or dis- charge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components shown in the design example will provide adequate compensation for most applications. a rough compensation check can be made by calculating the gain crossover frequency, f gco . g m(ea) is the error ampli? er transconductance, r c is the compensation re- sistor and feedback divider attenuation is assumed to be 0.8v/v out . this equation assumes that no feed-forward compensation is used on feedback and that c out sets the dominant output pole. fg r i cv gco m ea c limit out out = () ?? . ? ?? ? . 16 1 2 08
LTC3878 17 3878f applications information as a rule of thumb the gain crossover frequency should be less than 20% of the switching frequency. for a detailed explanation of switching control loop theory see applica- tion note 76. high switching frequency operation special care should be taken when operating at switching frequencies greater than 800khz. at high switching frequen- cies there may be an increased sensitivity to pcb noise which may result in off-time variation greater than normal. this off-time instability can be prevented in several ways. first, carefully follow the recommended layout techniques. second, use 2f or more of x5r or x7r ceramic input capacitance per amps of load current. third, if necessary, increase the bottom mosfet ripple voltage to 30mv p-p or greater. this ripple voltage is equal to r ds(on) typical at 25c ? i p-p . design example figure 7 is a power supply design example with the fol- lowing speci? cations: v in = 4.5v to 28v (12v nominal), v out = 1.2v 5%, i out(max) = 15a and f = 400khz. start by calculating the timing resistor, r on : r v vkhzpf k on 12 0 7 400 10 429 . .? ? select the nearest standard resistor value of 432k for a nominal operating frequency of 396khz. set the inductor value to give 35% ripple current at maximum v in using the adjusted operating frequency: l v khz a h 12 396 0 35 15 1 12 28 055 . ?. ? C . . select 0.56h which is the nearest value. the resulting maximum ripple current is: i v khz h v v a l 12 396 0 56 1 12 28 51 . ?. C . . choose the synchronous bottom mosfet switch and calculate the v rng current limit set-point. to calculate v rng and v ds , the ? term normalization factor (unity at 25c) is required to account for variation in mosfet on-resistance with temperature. choosing an rjk0330 (r ds(on) = 2.8m (nominal) 3.9m (maximum), v gs = 4.5v, ja = 40c/w) yields a drain source voltage of: vi i m ds limit ripple () () C. 1 2 39 figure 7. design example: 1.2v/15a at 400khz + run/ss LTC3878 boost 16 c b 0.22f m1 rjk0305dpb c vcc 4.7f c c1 220pf c c2 33pf d b cmdsh-3 l1 0.56h c out1 470f 2.5v s 2 c out2 100f 6.3v + c in1 10f 50v s 3 c in2 100f 50v v out 1.2v 15a 3878 f07 v in 4.5v to 28v 1 pgood r pg 100k r2 80.6k r c 12.1k r fb1 10.0k r1 10.0k tg 15 2 v rng sw 14 3 mode pgnd 13 4 i th bg 12 5 sgnd inv cc 11 6 i on v in 10 7 v fb nc 9 8 r on 432k r fb2 5.11k m2 rjk0330dpb c in1 : umk325bj106mm s 3 c out1 : sanyo 2r5tpe330m9 s 2 c out2 : murata grm31cr60j476m s 2 l1: vishay ihlp4040dz-11 0.56h c ss 0.1f
LTC3878 18 3878f v rng sets current limit by ? xing the maximum peak v ds voltage on the bottom mosfet switch. as a result, the average dc current limit includes signi? cant temperature and component variability. design to guarantee that the average dc current limit will always exceed the rated oper- ating output current by assuming worst-case component tolerance and temperature. the worst-case minimum intv cc is 5.15v. the bottom mosfet worst-case r ds(on) is 3.9m and the junction temperature is 80c above a 70c ambient with 150c = 1.5. set t on equal to the minimum speci? cation of 15% low and the inductor 15% high. by setting i limit equal to 15a we get 79mv for peak v ds voltage which corresponds to a v rng equal to 592mv: vaa m v ds 15 1 2 51 085 115 39 515 53 C?. ? . . . . . v v vv rng ds ?. .? 15 75 verify that the calculated nominal t j is less than the assumed worst-case t j in the bottom mosfet: p vv v amw t top j () 28 1 2 28 15 15 39 125 70 2 C. ?.?. . cwcw c 1 25 40 120 .?/ b ecause the top mosfet is on for a short time, an rjk0305dpb (r ds(on) = 10m (nominal) 13m (c miller = q gd /10v = 150pf, v boost = 5v), v gs = 4.5v, ja = 40c/w) is suf? cient. checking its power dissipa- tion at current limit with = 100c = 1.4: p v v amv a top () () 12 28 15 1 4 13 28 15 2 22 . ?.? () 2 5 150 25 2 12 3 400 0 . .. . pf khz 1 18 0 58 0 65 70 0 76 40 100 www tcwcw c j .. .?/ the junction temperatures will be signi? cantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary. select c in to give an rms current rating greater than 4a at 85c. the output capacitor c out1 is chosen for a low esr of 4.5m to minimize output voltage changes due to inductor ripple current and load steps. the output voltage ripple is given as: v i esr mmv out ripple l max ()() .? . () 51 45 23 however, a 0a to 10a load step will cause an output change of up to: v i esr am mv out step load () ?. () 10 4 5 45 optional 2 47f ceramic output capacitors are included to minimize the effect of esr and esl in the output ripple and to improve load step response. pc board layout checklist the LTC3878 pc board layout can be designed with or without a ground plane. a ground plane is generally pre- ferred based on performance and noise concerns. when using a ground plane, use a dedicated ground plane layer. in addition, for high current it is recommended to use a multilayer board to help with heat sinking power components. l the ground plane layer should have no traces and be as close as possible to the routing layer connecting the power mosfets. l place LTC3878 pins 9 to 16 facing the power compo- nents. keep components connected to pin 1 close to LTC3878 (noise sensitive components). l place c in , c out , mosfets, d b and inductor all in one compact area. it may help to have some components on the bottom side of the board. l use an immediate via to connect components to the ground plane sgnd and pgnd of LTC3878. use several larger vias for power components. l use compact switch node (sw) plane to improve cool- ing of the mosfets and to keep emi down. applications information
LTC3878 19 3878f l use planes for v in and v out to maintain good voltage ? ltering and to keep power losses low. l flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power component. you can connect the copper areas to any dc net. (v in , v out , gnd or to any other dc rail in your system). l place decoupling capacitor c c2 next to the i th and sgnd pins with short, direct trace connections. when laying out a printed circuit board without a ground plane, use the following checklist to ensure proper operation of the controller. these items are illustrated in figure 7. l segregate the signal and power grounds. all small-signal components should return to the sgnd pin at one point. sgnd and pgnd should be tied together underneath the ic and then connect directly to the source of m2. l place m2 as close to the controller as possible, keeping the pgnd, bg and sw traces short. l keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. l connect the input capacitor(s), c in , close to the power mosfets. this capacitor carries the mosfet ac current. l connect the intv cc decoupling capacitor c vcc closely to the intv cc and pgnd pins. l connect the top driver boost capacitor, c b , closely to the boost and sw pins. l connect the v in pin decoupling c f closely to the v in and pgnd pins. figure 8. LTC3878 layout diagram without ground plane applications information 16 15 14 13 12 11 10 9 c c2 bold lines indicate high current paths c c1 c ss r on r c r f 3878 f08 1 2 3 4 5 6 7 8 run/ss pgood v rng fcb i th sgnd i on v fb boost tg sw pgnd bg intv cc v in nc c b m2 m1 d1 d b c f c vcc c out c in v in v out + C + C LTC3878 l r1 r2 +
LTC3878 20 3878f typical applications 4.5v to 14v input, 1.2v/20a output at 300khz + run/ss LTC3878 boost 16 c b 0.22f m1 rjk0305dpb c vcc 4.7f c c1 330pf c ss 0.1f c c2 100pf d b cmdsh-3 l1 0.44h c out1 330f 2.5v s 3 c out2 100f 6.3v s 2 + c in1 10f 16v s 2 c in2 180f 16v v out 1.2v 20a 3878 ta02 v in 4.5v to 14v 1 pgood r pg 100k r2 57.6k r c 18k r fb1 10.0k r1 10.0k tg 15 2 v rng sw 14 3 mode pgnd 13 4 i th bg 12 5 sgnd inv cc 11 6 i on v in 10 7 v fb nc 9 8 r on 576k r fb2 5.11k c f 0.1f r f 1 m2 rjk0330dpb c in1 : tdk c3225x5r1c106mt s 2 c out1 : sanyo 2r5tpe330m9 s 3 c out2 : murata grm31cr60j107me39 s 2 l1: pulse pa0513.441nlt 4.5v to 24v input, 1.8v/10a output at 500khz + run/ss LTC3878 boost 16 c b 0.22f m1 fds8690 c vcc 4.7f c c1 1000pf c c2 100pf d b cmdsh-3 l1 0.8h c out1 330f 2.5v c out2 100f 6.3v + c in1 10f 25v c in2 56f 25v v out 1.8v 10a 3878 ta03 v in 4.5v to 24v 1 pgood r pg 100k r2 95.3k r c 10k r fb1 10.0k r1 10.0k tg 15 2 v rng sw 14 3 mode pgnd 13 4 i th bg 12 5 sgnd inv cc 11 6 i on v in 10 7 v fb nc 9 8 r on 511k r fb2 12.7k c f 0.1f r f 2.2 m2 fds8670 c in1 : tdk c3225x5r1e106mt c out1 : sanyo 2r5tpe330m9 c out2 : murata grm31cr60j107me39 l1: sumida cdep105np-0r8mc-50 c ss 0.1f
LTC3878 21 3878f typical applications 4.5v to 32v input, 1v/5a output at 250khz 4.5v to 28v input, 2.5v/5a output at 500khz + run/ss LTC3878 boost 16 c b 0.22f m1 bsc093n04ls m2 bsc093n04ls c vcc 4.7f c c1 1000pf c c2 100pf d b zlls1000 l1 2.2h c out1 330f 2.5v c out2 47f 6.3v + c in1 4.7f 50v c in2 22f 35v v out 1v 5a 3878 ta04 v in 4.5v to 32v 1 pgood r pg 100k r c 13k r fb1 10.0k tg 15 2 v rng sw 14 3 mode pgnd 13 4 i th bg 12 5 sgnd inv cc 11 6 i on v in 10 7 v fb nc 9 8 r on 576k r fb2 2.55k c f 0.1f r f 2.2 c in1 : murata grm32er71h475k c out1 : sanyo 2r5tpe330m9 c out2 : tdk c3216x5r0j476m l1: wurth 744311220 c ss 0.1f run/ss LTC3878 boost 16 c b 0.22f m1-1 1/2 si4816bdy m1-2 1/2 si4816bdy c vcc 4.7f c c1 1000pf c c2 100pf d b cmdsh-3 l1 2.2h c out 100f 6.3v s 2 + c in1 4.7f 50v c in2 22f 35v v out 2.5v 5a 3878 ta05 v in 4.5v to 28v 1 pgood r pg 100k r2 80.6k r c 8.2k r fb1 10.0k r1 10.0k tg 15 2 v rng sw 14 3 mode pgnd 13 4 i th bg 12 5 sgnd inv cc 11 6 i on v in 10 7 v fb nc 9 8 r on 715k r fb2 21.5k c f 0.1f r f 2.2 c in1 : murata grm32er71h475k c out : murata grm32er60j107m l1: wurth 744311220 c ss 0.1f
LTC3878 22 3878f typical applications 13v to 28v input, 12v/5a output at 300khz + run/ss LTC3878 boost 16 c b 0.22f m2 bsc093n04ls m1 bsc093n04ls c vcc 4.7f c c1 1000pf c c2 100pf d b cmdsh-3 l1 10h c out1 82f 16v + c in1 4.7f 50v c in2 22f 35v v out 12v 5a 3878 ta06 v in 13v to 32v 1 pgood 2.7m r c 20k r fb1 10.0k tg 15 2 v rng sw 14 3 mode pgnd 13 4 i th bg 12 5 sgnd inv cc 11 6 i on v in 10 7 v fb nc 9 8 r on 2.7m r fb2 140k c f 0.1f r f 2.2 c in1 : murata grm32er71h475k c out1 : sanyo 16svpa82maa l1: ihlp5050fd01 10h c ss 0.1f positive-to-negative converter, C5v/5a at 300khz + + run/ss LTC3878 boost 16 c b 0.22f m2 rjk0304dpb m1 rjk0304dpb c vcc 4.7f c c1 2200pf c c2 100pf d b cmdsh-3 l1 2.2h c out1 120f 6.3v s 3 c out2 10f 10v s 4 + c in1 4.7f 50v c in2 82f 25v v out C5v 5a 3878 ta07 v in 4.5v to 20v 1 pgood r c 15k r pg 100k r fb1 20.0k tg 15 2 v rng sw 14 3 mode pgnd 13 4 i th bg 12 5 sgnd inv cc 11 6 i on v in 10 7 v fb nc 9 8 r on 2.4m r fb2 105k c f 0.1f r f 2.2 c in1 : tdk c3225x5r1e106mt c out1 : kemet a700d127m006ate015 s 3 c out2 : murata grm31cr61a106ka01 s 4 l1: ihlp5050ez-01 2.2h c ss 0.1f v in 5v 12v 20v i out 5a 7.7a 9.1a
LTC3878 23 3878f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) s 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
LTC3878 24 3878f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2009 lt 0109 ? printed in usa related parts part number description comments ltc3608/ltc3609 8a/6a monolithic synchronous step-down dc/dc converters optimized for high step-down ratios, v in up to 18v/32v ltc3610/ltc3611 12a/10a monolithic synchronous step-down dc/dc converters optimized for high step-down ratios, v in up to 24v/32v ltc3708 dual, 2-phase, constant on-time no r sense synchronous step-down controller with output tracking fast transient response reduces c out , 4v v in 36v, 0.6v v out 6v, t on(min) < 83ns ltc3728 2-phase 550khz, dual synchronous step-down controller qfn and ssop packages ltc3770 no r sense synchronous step-down controller with voltage margining, pll and tracking 0.6v v out (0.9)v in , 4v v in 36v, i out up to 20a ltc3778 no r sense constant on-time synchronous step-down controller extremely fast transient response, t on(min) 100ns, 4v v in 36v, 0.8v reference ltc3811 dual, polyphase ? synchronous step-down controller, 20a to 200a differential remote sense ampli? er, r sense or dcr current sense ltc3823 constant on-time synchronous no r sense step-down controller with differential output sensing fast transient response, 4.5v v in 36v, 0.6v v out 0.9v in , tracking and pll synchronization ltc3824 low i q , high voltage current mode controller, 100% duty cycle, programmable operating frequency v in up to 60v, i out 5a, onboard bias regulator, burst mode operation, 40a i q , msop-10 package ltc3826/ltc3826-1 very low i q , dual, 2-phase synchronous step-down controllers 30a i q , 0.8v v out 10v, 4v v in 36v ltc3828 dual, 2-phase synchronous step-down controller with tracking up to six phases, 0.8v v out 5.25v, 4.5v v in 28v ltc3834/ltc3834-1 very low i q , synchronous step-down controller 30a i q , 0.8v v out 10v, 4v v in 36v lt3844 low i q , high voltage current mode controller with programmable operating frequency v in up to 60v, i out 5v onboard bias regulator, burst mode operation, 120a i q , sync capability, 16-lead tssop package lt3845 low i q , high voltage single output synchronous step-down dc/dc controller 1.23v v out 36v, 4v v in 60v, 120a i q ltc3850/ltc3850-1 ltc3850-2 dual 2-phase, high ef? ciency synchronous step-down controllers r sense or dcr current sense, 250khz to 780khz fixed operating frequency, 4v v in 30v, 0.8v v out 5.25v ltc3851/ltc3851-1 no r sense wide input range step-down controllers 4v v in 38v, very low dropout with tracking, dcr current sense, msop-16, ssop-16, 3mm 3mm qfn-16 ltc3853 triple output, multiphase synchronous step-down controller r sense or dcr current sensing, tracking and synchronizable ltc3879 no r sense constant on-time synchronous step-down controller extremely fast transient response, t on(min) = 43ns, 4v v in 38v, 0.6v reference ltm4600hv 10a complete switch mode power supply 92% ef? ciency, v in : 4.5v to 28v, true current mode control, ultrafast? transient response ltm4601ahv 12a complete switch mode power supply 92% ef? ciency, v in : 4.5v to 28v, true current mode control, ultrafast transient response polyphase is a registered trademark fo linear technology corporation. no r sense is a trademark of linear technology corporation.

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